Businesses and consumers alike want video monitors and projectors to display the crispest, most life-like images. Driven by this demand, traditional design blocks for multimedia products require larger, more complex chip designs. That leaves designers confronting major validation challenges during the integration of those complex blocks, and often disappointed consumers contending with low product quality and delays in new product introductions.

Quickturn, a Cadence company, has created environments specifically tailored for the development and verification of complex emerging applications for companies like SP3D Chip Design, a subsidiary of Philips Semiconductors that specializes in advanced 3-D graphics applications. This article shows how we shaved weeks off the verification of SP3D's LCD controller chip design.

The SP3D SA6714 SXGA triple-input TFT display controller performs all the needed functions for processing and measuring incoming data on behalf of an SXGA LCD monitor or projector. This sophisticated,million-gate chip features an elaborate clock-generation module with numerous multiplexers in the clock trees, five asynchronous clocks,14 variably sized RAMs and a DDR-RAM inter-face. The SAA6714 chip epitomizes the high-end consumer demand in today's electronics marketplace, where features like picture-in-picture, a dual video pipeline, keystone correction and image-enhancing dynamic noise reduction are fast becoming necessities.

From the outset, SP3D's goal was to develop an SXGA-capable product that would outperform competitors in speed, features and price. This meant producing a complex chip that would require comprehensive, yet efficient,verification. More important, a verification methodology had to catch all of the bugs the first time while still beating competitors to market.

When SP3D began development of its controller chip, it targeted a release date that would trump potential rivals without sacrificing quality. To achieve this, the company chose a Quickturn multimedia verification environment that uses the MercuryPlus N3000 emulation system and an enhanced version of Quickturn's high-performance Video SpeedBridge product.

Video SpeedBridge provides the required speed buffering and interfacing between the in-circuitemulator and the target hardware, allowing developers to verify their designs using real-world data, based on real-world data standards. Video SpeedBridge sources video data to the emulated design at emulation speeds. It captures data from the emulator, analyzes it and plays back video data on the monitor in near-real-time, allowing designers to test and debug designs. The enhanced version of Video SpeedBridge offers customers a variety of performance options at different price points. Performance ranges up to 2 MHz on the source side and up to 10 MHz on the capture side.

SP3D considered using simulation but judged it to be too slow, with test cases that were too small and of insufficient resolution. The SP3D SAA6714 design reached 700 kHz on average. SP 3 D believed that the complexity of the SAA6714 IC demanded an emulator that would accommodate the entire million-gate design and be able to evaluate the product's extensive capabilities -- live. Several emulation vendors were considered, but in the end, Quickturn and its Mercury Plus product were selected.

Starting from its specification, SP3D developed a C model as a “golden reference" and as a way of testing the functionality of its algorithms. This ensured that the RTL simulation and gate-level simulation were fed with the same test cases as the C model, and that the results would be comparable. As soon as it was confirmed that some of those basic tests had been passed,and that the netlist seemed relatively stable, SP3D was ready to start emulation for more in-depth debugging of the design. SP 3 D would begin tapeout once the three other verification methodologies -- RTL, gate-level and emulation -- had successfully matched the golden C model.

Since SP3D designers did not use Quickturn's HDL-ICE tool to map the RTL description of the SAA6714 design directly to the emulator format,the designers needed to synthesize their RTL to the gate-level format prior to going to emulation. Once the gate-level netlist had passed some basic functionality tests through simulation, the netlist was then ported to the emulator. After that was accomplished, SP3D accessed the chip via register writes as one of the steps in integrating with the emulator.

The designers verified basic chip functionality, then added the remaining Quickturn system components -- RGB SpeedBridge and the enhanced Video SpeedBridge -- to their emulation environment. The RGB SpeedBridge allows the designer to view how the image would look on a “real" device video projector LCD panel. The Video SpeedBridge, meanwhile, can capture, analyze and view data on the capture side and source data to the emulator on the source side.

To complete the emulation environment, SP3D used a proprietary target system containing custom boards -- DDR RAM, clock, PLX IFC -- along with a PLX SpeedBridge and a target PC. The PLX SpeedBridge does simple PCI-to-local and -I2C bus conversion as well as slow down the I2C signals to the speed of the emulator. The PLX IFC board acts as an interface chip between the emulator and the PLX SpeedBridge as well as the clock source to the design in the emulator. The target PC contains the necessary drivers and software to help generate the image data.

Once the environment was completed, SP3D began running more complex tests to verify the 3-D graphics controller chip within the emulator while interactively viewing and analyzing the images using RGB SpeedBridge and Video SpeedBridge.

Two developers dedicated to the verification process were added to the original development team of 18 people. The team transferred the design to Mercury Plus over a two-to three-week period, hampered in part by a cable problem due to the then-beta status of the software. A portion of that time also was spent modeling the RAMs and ROMs in the design for use within the emulator. The design was compiled in just over three hours for Mercury Plus on a dedicated HP J6000 with two processors and 4 Gbytes of RAM.

In measuring the benefits of an emulator, compile time is just as important as the raw performance you can attain by running the emulator. Compile time performance is a direct indicator of how many design turns you can achieve in a day as you uncover and fix more bugs within your design. Since adopting its own custom FPGA designed primarily for emulation, Quickturn has dramatically improved its compile time and thus increased significantly the number of design turns achievable within a day.

The SP3D team found 10 serious bugs in the controller chip, five of which were in its main control logic and considered absolute killers for the design. If not caught by Mercury Plus, each of the five killer bugs might have resulted in another spin of silicon. That's no small matter considering that a spin can take two to three months, exceed the target time-to-market date and force another expensive design cycle.

SP3D continues to use Mercury Plus to emulate its designs and plans to incorporate Quickturn's HDL-ICE software into its verification flow to streamline the process even more. Quickturn's HDL-ICE enables users to map RTL directly to the emulator. That means SP3D will be able to employ the emulator much earlier in the design cycle, speeding the process even more. Currently, SP3D has to translate VHDL/Verilog RTL code to a gate-level netlist, which can take a considerable amount of time using a commercial synthesis tool. On average, HDL-ICE can synthesize a 4-million-gate RTL design in 30 minutes. SP3D estimates that its custom Quickturn verification environment slashed four to six weeks off the verification of the complex multimedia chip project.